Díaz-Madrid, José-Ángel

Información Personal:

Cargo: Profesor CUD Tiempo Parcial
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Teléfono o fax: 968189936
Localización: Edificio CUD, Despacho 33
Descripción:

 

diazmadrid

Dr. Ing. José Ángel Díaz Madrid

Centro Universitario de la DefensaSan JavierMurciaEspaña

TELÉFONO:968189936 E-MAIL: jose.diaz@cud.upct.es

PROFILE              José Ángel Díaz Madrid was born in Cartagena, Spain. He received his Technical Industrial in Electrical Engineering Degree from Universidad de Murcia, and then he obtained his M.S degree in Automation and Industrial Electronic Engineering and in 2007, and Ph.D. Degree in Electronic Engineering 2017 from Universidad Politécnica de Cartagena (Spain). He is temporally a full-time Lecturer and Researcher at the Centro Universitario de la Defensa (CUD-UPCT) de San Javier (University Centre of Defense at the Spanish Air Force Academy). He is professor for teaching subjects: Electrical Technology and Automation and Electronic Instrumentation" and coordinating the external practice for the students of the CUD-UPCT of San Javier. His main research interests are mixed-signal ASIC design for applications such as CIS CMOS Sensors and acquisition data systems and sensors. Currently, he is involved national public research projects and he has a closed collaboration with Univesidad Politécnica de Cartage, National Center of Microelectronic in Sevilla, Universidad de Santiago de Compostela and Fraunhofer Institute IIS in Germany.

EDUCATION         2017 Ph. Degree with International Mention

Technical University of Cartagena

2001 Engineer in Automation and Industrial Electronic

Technical University of Cartagena

1997 Industrial Technical Engineer in Electricity

University of Murcia

PROFESIONAL

EXPERIENCE      

From 2017: Centro Universitario de la Defensa en San Javier

Full-time lecturer in electrical, electronic and automation engineering

From 2009 to 2016: Centro Universitario de la Defensa en San Javier

Partial-time lecturer in electrical, electronic and automation engineering

From 2009 to 2017: Bionet Servicios Técnicos S.L

Departmental Coordinator of Innovation and Automation Engineering

From 2009 to 2010: Universidad Politécnica de Cartagena

Partial-time lecturer in analog and digital electronic

From 2001 to 2008: Fraunhofer Institute IIS

Mixed-signal Integrated Circuit designer.

TEACHING         GRADO EN INGENIERÍA DE ORGANIZACIÓN INDUSTRIAL

(Centro Universitario de la Defensa en San Javier)

Tecnología Eléctrica

2º Curso, 1º Cuatrimestre y Obligatoria

Automatización e Instrumentación Electrónica

2º Curso, 1º Cuatrimestre y Obligatoria

Tutorización de prácticas de empresa

5º Curso, 1º y 2º Cuatrimestre y Obligatoria

TECHNICAL

CAPABILITIES      

Develop and research in analog and digital circuits for ASICs for several applications such as:  

- Analog to digital conversion ASICs, research in CIS CMOS sensors.

- Develop specifications, test benches, schematics for designs and applications.

- Consulting for perform post-layout simulations in CHIPs.

Consulting for perform design engineering activities for the development of products, processes and equipment in support.

- Support validation and product launch activities for new devices.

- Develop specifications, test benches, schematics for designs and applications for PCBs.

 

 photochip

Photochip  (Area=1 mm²)

 

          

 

RESEARCH

PROJECTS          

Project Name:

Síntesis de convertidores ADC de altas prestaciones. Desarrollo de modelos en VHDL-AMS. 03094/PI/05

Budget:

32.400 euros

Organization:

Fundación Séneca. Comunidad Autónoma de la Región de Murcia

Date:

01/01/2006     Duration: 2 Years

Project Name:

“Herramientas y dispositivos inteligentes para el control de la calidad asistencial en procesos de seguimiento integrado intra/extrahospitalario de pacientes: Dispositivo para registro de señales PGCR. TIN2006-15460-C04-04”

Budget:

42.350 euros

Organization:

Ministerio de Educación y Ciencia

Date:

: 01/10/2006   Duration: 3 Years

Project Name:

MONDEGO: Sistema de visión en un único chip para el desarrollo de aplicaciones de visión distribuida en red. TEC2012-38921-C02-0

Budget:

 

Organization:

Ministerio de Economía y Competitividad, dentro del Plan Nacionalde I+D+i

Date:

01/01/2013 2 Years

Project Name:

Diseño e implementación de arquitecturas adaptadas para la conversión analógico-digital y el procesamiento de imágenes a niveles bajo, Referencia: TEC2015-66878-C3-2-R

Budget:

129.833,00 Euros

Organization:

Ministerio de Economía y Competitividad, dentro del Plan Nacionalde I+D+i

Date:

01/01/2016 - Now

Project Name:

Desarrollo de la electrónica de control para detectores de alta sensibilidad y bajo nivel de ruido esenciales para instrumentación astronómica de alta resolución angular. Referencia: 08801/PI/08

Budget:

38.700 Euros

Organization:

Ministerio de Economía y Competitividad, dentro del Plan Nacionalde I+D+i

Date:

01/01/2009- 1 Year

Project Name:

Infraestructura Sensorial Domiciliaria de Bajo Consumo para el Seguimiento de Personas Mayores. Referencia: 15303/PI/10

Budget:

 

Organization:

Fundación Séneca

Date:

01/01/2011- 1 Year

Project Name:

TSDK: Integración de amplificadores de señal en chip de cámaras de video.

Budget:

600.000 Euros

Organization:

Fundación Séneca

Date:

01/08/2004- 1 Year

Project Name:

PROFCAM: Integración de un driver de alta velocidad para proyector de imágenes.

Budget:

 

Organization:

Consejería de investigación de Baviera. Muenchen.

Date:

01/01/2004- 1 Year

PUBLICATIONS

IN JCR                 Authors: Jose Angel Diaz Madrid, Juan Hinojosa y Ginés Domenech.

Title: Fuzzy Logic technique for accurate analog circuits macromodels sizing

Editorial: Internacional Journal of Circuit Theory and Applications, Volume 38, pages 307–319, April 2010 doi: 10.1002/cta.575

JCR classification: Engineering, Electrical & Electronic.

Author(es): Gines Domenech, Jose Angel Diaz Madrid, Ramón Ruiz-Merino

Title: Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels

Editorial: Internacional Journal of Circuit Theory and Applications

Volume 41, pages 732–742, April 2011, doi: 10.1002/cta.820

JCR classification: Engineering, Electrical & Electronic

Authors: Domenech-Asensi, G.; Carrillo-Calleja, J.; Illade-Quinteiro, J.; Martinez-Viviente, F.; Diaz-Madrid, J.; Fernandez-Luque, F.; Zapata-Perez, J.; Ruiz-Merino, R.; Dominguez-Puertas, M.

Title: Low frequency CMOS band pass filter for PIR sensors in wireless sensor nodes

Editorial: Sensors Journal, IEEE vol.PP, no.99, pp.1,1, doi: 10.1109/JSEN.2014.2333538

JCR classification: Engineering, Electrical & Electronic.

Authors: José Angel Díaz-Madrid and Ginés Doménech-Asensi and Matthias Oberst

Title: A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

Editorial: International Journal of Electronics, Volume: 103, pages 1998-2012, 2016, Year: 2016 Nº pages: 12, doi = {10.1080/00207217.2016.1175032}

JCR classification: Engineering, Electrical & Electronic.

Authors: Ginés Doménech Asensi, Ramon Ruiz Merino, Juan Zapata, Jose Angel Diaz-Madrid.

Title: An all-hardware implementation of the subpixel refinement stage in SIFT algorithm.

Editorial: International Journal of Circuit Theory and Applications. Year: 2018

JCR classification: Engineering, Electrical & Electronic.

OTHER

PUBLICATIONS  

Authors: Ginés Doménech Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz Madrid

Title: Current mode CMOS synthesis of a motor-control neural system

Editorial: Lecture Notes in Computer Science

Clave: 2687    Year: 2003      Nº pages: 25-32

Authors: Jose Alejandro López Alcantud, José Ángel Díaz Madrid, Hans Hauer, Ramón Ruiz Merino

Nº autores: 4

Title: An analogue current–mode hardware design proposal for preprocessing layers in ART–based neural networks

Editorial: Lecture Notes in Computer Science

Clave: 2687    Year: 2003      Nº pages: 97-104

Authors: José Ángel Díaz Madrid, Pedro Monsalve, Juan Hinojosa, María Victoria Rodellar , Ginés Domenech

Title: Improvement of ANNs performance to generate fitting surface for analog CMOS circuits.

Editorial Lecture Notes in Computer Science

Clave 4528   Year 2007 Nº de pages ISSN 19-27

Authors Doménech Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz Madrid

Title CMOS analog Implementation of a Simplified Spinal Cord Neural Model

Editorial Proceedings of SPIE

Clave 5119   Year 2003 Nº de pages 24-34

Authors J.A. Díaz-Madrid, G. Doménech-Asensi, Ramón Ruiz, H.Neubauer

Nº autores: 4

Title: Influence of the amplifier sharing tecnique in pipeline analog-to-digital converters (ADCs)

Editorial Revista VI TelecoForum UPCT 2008 (ISSN:)

Clave ………   Year 2006 Nº de pages ISSN (1698-2924)

Authors J.A. Díaz-Madrid, G. Doménech-Asensi, Ramón Ruiz, H.Neubauer

Title: Current-mode implementation of processing modules in ART-based neural networks

Editorial: Proc. SPIE 5119, Bioengineered and Bioinspired Systems, 35 (April 21, 2003); doi:10.1117/12.499188; http://dx.doi.org/10.1117/12.499188

CONFERENCES

Authors: Diaz-Madrid, Domenech-Asensi, G.; Rodriguez-Bermudez, G., Carmona Galan,R.

Title: Implementación de un ADC reconfigurable de bajo consumo de tipo cíclico y topología pipeline en el proceso tecnológico C35B4.

Year: 2013

Conference: Conference Nacional de I+D en Defensa y Seguridad

Level (N/I): N

Place: Madrid, España

Authors: Diaz-Madrid, Domenech-Asensi, G.; Rodriguez-Bermudez, G., Carmona Galan,R.

Title: Técnicas para la reducción del consumo en ADCs de topología pipeline.

Year: 2016

Conference: Conference Nacional de I+D en Defensa y Seguridad

Level (N/I): N

Place:San Javier, España

Authors: Gines Doménech-Asensi, José Ángel Díaz Madrid, Juan Hinojosa, Ramón Ruiz

Title: Accurate and Reusable macromodeling technique using a fuzzic logic approach

Year: 2008

Conference: IEEE International Symposium on Circuits and Systems

Level (N/I): I

Place:Seatle, EEUU

Authors: J.A. Díaz-Madrid, H. Neubauer, Ginés Domenech, Ramón Ruiz

Title: Comparative analysis of two operational amplifier topologies for a 40MS-s 12-bit pipelined ADC in 0.35um CMOS

Year: 2008

Conference: International conference on IC Design and Technology

Level (N/I): I

Place:Grenoble, Francia

Authors: Eugeni García Moreno, Rodrigo Picos, Kay Suenaga, David Camarero, Jose Angel Diaz Madrid, H. Hauer, Gines Domenech

Title: Predictive Test of a simple and hold circuit

Year: 2008

Conference: XXII Conference on Design of Circuits and Integrated Systems

Level (N/I): I

Place:Grenoble, Francia

Authors: Ginés Doménech, Ramón Ruiz Merino, José Ángel Díaz Madrid, Juan Zapata Pérez

Title: VHDL-AMS description of a Biosignal monitor integrated circuit

Year: 2009

Conference: XXIV Conference on Design of Circuits and Integrated Systems

Level (N/I): I

Place:Zaragoza

Authors: Diaz-Madrid, J.A; Neubauer, H.; Hauer, H.; Domenech-Asensi, G.; Ruiz-Merino, R.

Title: Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

Year: 2009

Conference: Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09

Level (N/I): I

Place:Niza, Francia

Authors: J.A. Díaz-Madrid, Ginés Domenech, Ramón Ruiz

Title: Evaluation of VHDL-AMS models of a high performance ADC

Year: 2007

Conference: IEEE International Symposium on Industrial Electronics

Level (N/I): I

Place:Vigo, España

Authors: J.A. Díaz-Madrid, G. Doménech-Asensi, J.A. López-Alcantud, H. Neubauer

Title: VHDL-AMS Model of a 40M/S 12 Bits Pipeline ADC

Year: 2006

Conference: Intl. Conference Mixed Design of Integrated Circuits and Systems,

Level (N/I): I

Place: Gdnya, Polonia

Authors: J.A. Díaz-Madrid, G. Doménech-Asensi, J.A. López-Alcantud, H. Hauer

Title: Parametrizable VHDL-AMS model of a transconductance amplifier

Year: 2007

Conference: XXII Conference on Design of Circuits and Integrated Systems

Level (N/I): I

Place: Sevilla

Centro Universitario de la Defensa • San Javier • Murcia • España

Publicaciones